1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device having a low-resistance tungsten line and to a method of manufacturing such a device.
2. Description of the Related Art
By improving the sensitivity of the sense amplifier used in dynamic random access memories (DRAMs), it is possible to more accurately sense and amplify the data stored in cells of the memory. The sensitivity can be improved by increasing the voltage difference, ΔV, at the input of the sense amplifier. The difference voltage, ΔV, is proportional to the supply voltage VCC, but is inversely proportional to the bit line loading capacitance (Cb).
The bit line loading capacitance includes the capacitance between the bit line and the substrate, the capacitance between the bit line and the word line, the capacitance between bit lines, and the capacitance between the bit line and a storage node contact plug. In particular, the capacitance between the bit line and the storage node contact plug has a great influence upon the bit line loading capacitance.
In order to reduce the capacitance between the bit line and the storage node contact plug, it is desirable to reduce the overlapping area between the bit line and the storage node contact plug. This can be accomplished by reducing the thickness of the bit line. However, reducing the thickness of the bit line increases the resistance of the bit line, resulting in a degradation of the operating speed of the semiconductor memory devices.
To reduce parasitic capacitance and to have a bit line with a small thickness, it has been suggested that a low-resistance metal layer be used as a bit line. Among such metal layers, a tungsten layer that is thermally stable and has a relatively low resistance has been frequently used as a bit line. A technique of forming a bit line of tungsten is disclosed in U.S. Pat. No. 6,563,162 granted to Han et al.
Hereinafter, such a bit line formed of tungsten will be briefly described with reference to FIG. 1. As shown in FIG. 1, an interlayer insulating layer 20 is formed on a semiconductor substrate 10 in which conductive regions, e.g., a MOS transistor (not shown) having a gate, a source, a drain and a contact pad (not shown) that contacts the source and drain of the MOS transistor, are formed. To expose the drain (not shown) of the MOS transistor or the contact pad that contacts the drain of the MOS transistor, the interlayer insulating layer 20 is etched to form a contact hole H.
A Ti layer 30 and a TiN layer 40 are formed on the interlayer insulating layer 20 and along the surface of the contact hole H. The Ti layer 30 and the TiN layer 40 can be formed using chemical vapor deposition (CVD). Using CVD they can be formed with a conformal thickness on the surface of the resultant structure of the etching. When depositing the Ti layer 30 and the TiN layer 40 using CVD, TiCl4 can be used as the source of Ti.
A tungsten (W)—nucleation layer is formed on the TiN layer 40, and then a bulk tungsten layer 50 is deposited on the tungsten (W)—nucleation layer. Predetermined parts of the bulk tungsten layer 50 and the tungsten (W)—nucleation layer are patterned. As a result, a bit line is formed.
As the capacity of semiconductor memory devices reaches up to 1 giga bits, the design rules of semiconductor memory devices drastically decrease. As a result smaller width bit lines are needed. When the width of bit lines is decreased, the resistance of the bit lines increases and the increase in resistance has an influence upon the operating speed of semiconductor memory devices.
Furthermore, if the thickness of a bit line is increased to reduce the resistance of the bit line, the capacitance of the bit line increases. Consequently, the sensitivity of the sense amplifier decreases. It is, in general, difficult to achieve a low-resistance bit line without increasing the capacitance of the bit line and therefore decreasing the sensitivity of the sense amplifier.